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    • 专利摘要:
    DRIVE SYSTEM, AND, COMPUTER-READABLE MEDIUM. Exemplary embodiments disclose a drive system including a machine including a plurality of phases and configured to generate power based on a plurality of phase currents, each respectively associated with a plurality of phases and a direct current (DC) bus. operatively, connected to the machine. The DC bus includes a high-side line, a low-side line and an inverter including a plurality of switching systems, operatively connected between the high-side and low-side lines, the plurality of switching systems, each configured to emit a respective one of a plurality of phase currents. The drive system also includes a controller, operatively connected to the DC bus and the machine, the controller configured to determine whether the fault exists in the drive system based on the plurality of phase currents and the voltage of the DC bus, the DC bus voltage being a voltage between the high-side and low-side lines.
    公开号:BR112013021649B1
    申请号:R112013021649-2
    申请日:2012-01-23
    公开日:2021-04-20
    发明作者:Brij Nadan Singh；Chris J. Tremel；Alan K. Gilman
    申请人:Deere & Company；
    IPC主号:
    专利说明:

    FIELD
    [001] Exemplary modalities refer to a machine systems powered by pre-drive diagnostics inverter for real-time fault detection, such as in the field of hybrid and electric vehicles and equipment. FUNDAMENTALS
    [002] It is known for a drive system for a hybrid or electric vehicle to have a mechanism (eg, internal combustion engine), a generator coupled to the mechanism, a direct current (DC) bus, and an engine. The DC bus is electrically coupled between the generator and the engine to operate one or more elements of the vehicle. A converter is electrically coupled between the generator and the DC bus and is controlled to convert Alternating Current (AC) power to DC power during generator generation and DC power to AC power during engine running. The motor can be a Switched Reluctance (SR) motor, a Permanent Magnet (PM) AC Motor, or an AC Induction Motor.
    [003] In an inverter powered drive system, a power inverter is electrically coupled between the DC bus and the motor and is controlled to convert DC energy from the DC bus to AC energy during motor and motor operation. to convert AC power to DC power during motor electrical braking. On vehicles with regenerative braking, the inverter also takes energy from the engine (now acting as a generator) and stores it in the batteries. A voltage sensor is electrically coupled to the DC bus to sense a DC bus voltage and output a DC bus voltage signal indicative of it. A current sensor detects a motor phase current and outputs a phase current signal indicative of it. A control system is electrically coupled to the voltage sensor and the current sensor to receive signals from sensors pertaining to system operation.
    [004] In an inverter powered electrical drive system, it can be appreciated that a variety of faults can occur in the various control and power components used in the systems, such as Insulated Gate Bipolar Transistors (IGBTs) in inverters, diodes in inverters, electrical machines, motor windings, DC bus capacitors, power cables, cables between inverters and electrical machines, etc. SUMMARY
    [005] Exemplary modalities propose a new control and monitoring technique for inverter powered machine systems. Pre-start diagnostics of electrical machinery done at low voltage levels can detect incipient failures before the system is operated at full power, significantly reducing maintenance cost and the risk of unexpected high voltage failures. In the example modalities, the fault can include an open circuit or a defect and is not limited to these two types of faults.
    [006] Exemplary modalities disclose at least two different methods that can be used for system pre-trigger diagnostics. A first method, which can be used for PM, Induction, or SR motors, uses measurements of perceived signal levels to determine if there is a fault in the system. It should be understood that "signal level" can refer to either a measured phase voltage or a measured phase current. It is possible to convert a measured phase voltage to a phase current with a transconductance amplifier or transresistance amplifier (eg operational amplifier plus a resistor). For reasons of simplicity, the first method is described using phase currents measured as signal levels. However, it should be understood that the first method can be implemented using measured phase voltages.
    [007] A second method, for systems having PM, Induction, or SR motors, uses perceived voltage measurements at the AC midpoint voltage measured between or the similar high-side and low-side devices on a leg of the drive against the negative DC bus to determine if there is a system fault. The perceived voltages are processed in the Analog to Digital Converter (ADC) which is built into the control system's Gate Operating Mechanisms. This data is considered as ADC count data. This method compares the ADC count data with the switching signals from the devices to identify and troubleshoot the system.
    [008] Additionally, the pre-existing presence of a control system and voltage and current sensors in the drives used for standard operation means that coding monitoring algorithms for pre-drive diagnostics can be implemented with little incremental cost, and typically require little more than a software update or a software handler.
    [009] By passing on the information provided by pre-start diagnostics and monitoring to confirm machine conditions and identify failures, and future failures, catastrophic and cascading system failures can be prevented, and thereby save significant money and prevent system downtime.
    [0010] The detection of faults in inverter driven machines is challenging due to the noise created by the high switching frequency. However, the cost savings of detecting and preventing catastrophic failures make pre-trigger diagnostics worth developing such methods.
    [0011] At least one exemplary modality provides a drive system including a machine including a plurality of phases and configured to generate power based on a plurality of phase currents, each respectively associated with a plurality of phases and a current bus. continuous (CC), operatively connected to the machine. The DC bus includes a high-side line, a low-side line, and an inverter including a plurality of switching systems, operatively connected between the high-side line and the low-side line, a plurality of systems. switches, each configured to output a respective one of a plurality of phase currents. The drive system also includes a controller, operatively connected to the DC bus and the machine, the controller configured to determine if the fault exists in the drive system based on a plurality of phase currents and a voltage of the DC bus. DC, the DC bus voltage being a voltage between the high-side line and the low-side line.
    [0012] At least another exemplary modality provides a drive system including, a machine including a plurality of phases and configured to generate power based on a plurality of phase currents, each respectively associated with a plurality of phases and a busbar. direct current (DC), operatively connected to the machine. The DC bus includes a high-side line, a low-side line, and an inverter including a plurality of switching systems, operatively connected between the high-side line and the low-side line, a plurality of of switching systems, each configured to output a respective one of a plurality of phase currents and a voltage. The drive system also includes a controller, operatively connected to the DC bus and the machine, the controller configured to respectively apply voltages to a plurality of switching systems, the output voltages of a plurality of phase currents respectively with based on the applied voltages. The controller includes an analog to digital converter (ADC) configured to measure voltages emitted by a plurality of switching systems, generating count data based on the measured voltages. The controller is configured to determine if a fault exists in the drive system based on the counter data.
    [0013] At least one other exemplary embodiment discloses a computer-readable medium, when running on a computer, configured to instruct the computer to determine whether a fault exists in a drive system based on a plurality of phase currents and a voltage of the DC bus. The drive system includes a machine including a plurality of phases and configured to generate power based on a plurality of phase currents, each respectively associated with a plurality of phases, a direct current (DC) bus, operatively, connected to the machine. The DC bus includes a high-side line, a low-side line, the DC bus voltage being a voltage between the high-side line and the low-side line, and an inverter including a plurality of switching systems, operatively, connected between the high-side line and the low-side line, a plurality of switching systems, each configured to emit one of a plurality of phase currents. BRIEF DESCRIPTION OF THE DRAWINGS
    [0014] Exemplary modalities will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. FIGS. 1-6 represent non-limiting exemplary embodiments as described herein.
    [0015] FIG. 1 is a diagrammatic view showing a drive system for a vehicle according to an example embodiment; FIG. 2 is a diagrammatic view of control and electrical portions of the drive system of Fig. 1 and current measurements according to an example embodiment; FIG. 3 is an enlarged diagrammatic view showing power flow through a section of a power inverter when supplying positive and negative current to a motor in accordance with an example embodiment; FIGS. 4A-4C illustrate flowcharts of a diagnostic method according to an example embodiment; FIG. 5 is a diagrammatic view of electrical portions of a drive system and current measurements used for a PM or Induction machine according to an example embodiment; and FIG. 6 is a diagrammatic view of electrical portions of a drive system and current measurements used for an SR machine system according to an example embodiment. DETAILED DESCRIPTION
    [0016] Several exemplary embodiments will now be described more fully with reference to the accompanying drawings in which some exemplary embodiments are illustrated.
    [0017] Consequently, while exemplary embodiments are capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will be described in detail here. It should be understood, however, that there is no intention to limit the exemplary embodiments to the particular disclosed forms, but rather, the exemplary embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of the claims. Like numbers refer to like elements throughout the description of figures.
    [0018] It will be understood that although the terms first, second, etc. can be used here to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish each element from another. For example, a first element could be called a second element, and similarly a second element could be called a first element, without departing from the scope of the example modalities. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
    [0019] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a similar way (eg, “between” versus “directly between”, “adjacent” versus “directly adjacent,” etc.). The terminology used here is for the purpose of describing particular modalities only and is not intended to be limiting of the exemplary modalities.
    [0020] As used here, the singular forms of "a", "an", "the" and "a" are intended to include the various forms as well, unless the context clearly indicates otherwise. It will further be understood that the terms "comprises", "characterized by the fact of comprising", "includes" and/or "including", when used herein, specify here the presence of characteristics, integers, steps, operations, elements and/or components placed, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
    [0021] It should also be noted that in some alternative implementations, the functions/acts noted may occur outside the order denoted in the figures. For example, two figures shown in succession may in fact be performed substantially concurrently or may sometimes be performed in reverse order, depending on the functionality/act involved.
    [0022] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of simple qualifications in the technique to which the exemplary modalities belong. It will be further understood that terms, eg those defined in commonly used dictionaries, are to be interpreted as having a meaning that is consistent with their meaning in the context of the relevant technique and will not be interpreted in an idealized or excessively formal sense unless expressly so defined here.
    [0023] Portions of the example embodiments and corresponding detailed description are presented in terms of software, or algorithms and symbolic representations of operation on data bits within a computer memory. These descriptions and representations are those through which those of simple qualification in technique effectively convey the substance of their work to others of simple qualification in technique. An algorithm, as the term is used here, and as it is used in general, is designed to be a sequence of self-consistent steps leading to a result. Steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of an optical, electrical, or magnetic signal capable of being stored, transferred, combined, and otherwise manipulated. It has sometimes proved convenient, mainly for reasons of common usage, to refer to these signs as bits, values, elements, symbols, characters, terms, numbers, or the like.
    [0024] In the following description, illustrative modalities will be described with acts of reference and symbolic representations of operations (e.g., in the form of flowcharts) that can be implemented as a program module or functional processes including routines, programs, objects, components, data structures, etc., that perform particular tasks or implement abstract data types and can be implemented using existing hardware. Such existing hardware may include one or more Central Processing Units (CPUs), digital signal processors (DSPs), application-specific integrated circuits, field programmable gate arrays (FPGAs) computers, or the like. It should be kept in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to those quantities. Unless specifically stated otherwise, or as is apparent from the discussion, terms such as “processing” or “computing” or “calculation” or. "determination" or "display" or the like, refers to the action and processes of a computer system, or similar electronic communication device, that manipulate and transform data represented as physical electronic quantities within the records and memories of the computer system in other data similarly represented as physical quantities within the memories or registers of the computer system or other such information store, display or transmission devices.
    [0025] Note also that the software implemented aspects of the example modalities are typically encoded in some form of tangible (or recording) storage medium or implemented over some type of transmission medium. Tangible storage media can be magnetic (eg, a floppy disk or hard disk) or optical (eg, a compact disk read-only memory, or “CD ROM”), and can be accessible random or read-only.
    [0026] Similarly, the transmission medium may be twisted pairs of wire, coaxial cable, optical fiber, or some other suitable transmission medium known in the art. Exemplary modalities are not limited by these aspects of any given implementation.
    [0027] FIG. 1 illustrates an inverter powered drive system 12 for a hybrid or electric vehicle to have a mechanism 20 (e.g., internal combustion engine), a generator 24 coupled to the mechanism 20, and a direct current (DC) bus 28 electrically coupled between generator 24 and an engine 32. Mechanism 20 provides motive power for a vehicle. Typically, generator 24 may take from a three-phase internal permanent magnet brushless synchronous generator having three phase windings, or other suitable form. Motor 32 can be a reluctance (SR) motor, a Permanent Magnet (PM) AC Motor, or an AC Induction Motor.
    [0028] The drive system 12 of the example embodiments is suitable for diagnosing, identifying and classifying a fault of an inverter (eg a power inverter 30) in real time or during an inverter operating mode, as opposed to a non-operational pre-test mode. In an operational mode, the inverter (eg, power inverter 30) is capable of converting direct current into one or more alternating current signals for application to machine 177 or motor to control machine or motor 32. In test mode , the inverter does not supply or emit one or more alternating current signals for application to the machine or motor 32.
    [0029] The DC bus 28 may have a converter 26 electrically coupled between the generator 24 and the motor 32 to convert alternating current (AC) energy to DC energy during a generator 24 generation mode of operation (ie conversion of mechanical energy from a power source to electrical energy to power the DC bus 28), and DC energy to AC energy during generator motor operation 24 (ie removing electrical energy from the DC bus 28 and converting -a into mechanical energy for the energy source). The DC bus 28 can have the power inverter 30 (e.g., a multi-phase inverter) electrically coupled between the converter 26 and the motor 32 to convert DC power from the DC bus 28 to AC power during operation of the motor 32 and to convert AC power to DC power during braking of the engine 32. The drive system 12 may include an electronic braking module 22 to dissipate electrical energy from the DC bus 28. In vehicles with an electronic braking module braking 22 (ie regenerative braking), inverter 30 also takes energy from motor 32 during braking and stores it in batteries (not shown).
    [0030] A voltage sensor 36 (shown in Fig. 2) is electrically coupled to the DC bus 28 to sense a DC bus voltage and output a DC bus voltage signal indicative of the same. A current sensor 38 is electrically coupled to the motor 32 to detect a phase current from the motor 32 and output a phase current signal indicative thereof. A control system 40 is electrically coupled to voltage sensor 36 and current sensor 38 to receive signals from sensors pertaining to the operation of the system. The drive system 12 may have a current sensor 38 for each phase of the motor 32. As such, if the motor 32 has a plurality of phases (e.g., three), the drive system 2 will typically have a plurality of current sensors (e.g., three), each current sensor 38 being electrically coupled to the respective phase of the motor 32 to detect the respective phase current of the motor 32 and output a respective phase current signal indicative thereof. The control system 40 is electrically coupled to each of the current sensors 38. Additionally, it can be appreciated that the drive system 12 may have more than one motor 32 and appended inverter 30 and built-in current current sensor(s) 38 in it, although only one is shown in Fig. 1.
    [0031] Referring to Fig. 2, details of the electrical components of the drive system 12 can be seen in greater detail. The DC bus 28 has a positive DC power rail (high side line) 44 and a negative DC power rail (low side line) 46. In the drive system 12 under normal operation, the nominal voltage of the bus is of DC 28 between positive and negative DC power rails 44, 46 may be, for example, 700 Volts DC. However, it should be understood that the rated voltage can be greater than or less than 700 volts DC.
    [0032] The power converter 26 can be configured as an AC to DC converter to convert three-phase AC power from generator 24, which may be a three-phase permanent magnet (PM) generator, to DC power for the DC bus 28, and vice versa. The digital circuit voltages at power converter 26 to power generator 24 are denoted as Vdig_1 for phase 1 voltage, Vdig_2 for phase 2 voltage, and Vdig_3 for phase 3 voltage. Vdig_1, Vdig_2 and Vdig_3, two switching packets 84 are placed across the DC power supply, and are turned on and off to generate the three phases from the motor power converter 26 to the power generator 24. Each packet of switching 84 includes a diode 84-1 and an insulated bipolar junction transistor (IGBT) 84-2. Respective switching packets 84 may be coupled to a respective one of the phase windings of the generator 24 to convert AC power from the respective winding to DC power on the DC bus 28 between the positive DC power rail 44 and the rail of negative DC power 46. When the appropriate voltage is applied to the base (port) of an IGBT 84-2 of the power converter 26, the IGTB 84=2 can be activated and the collector can be electrically coupled to the emitter to supply power electrical, The proper voltage depends on an evaluation of the IGBT 84-2. For example, 14V can be applied at the base with respect to an emitter of the IGBT 84-2 to activate the IGBT 84-2. Negative 8V can be applied at the base with respect to the emitter to disable the IGBT 84-2. Power converter 26 can be operated in reverse if generator 24 is to operate as a motor.
    [0033] Although IGBT refers to an insulated gate bipolar transistor, in any phase of the inverter 30, the high-side switching transistor (eg 94-2a) and the low-side switching transistor (eg, 94-2b) may comprise field effect transistors, complementary metal oxide semiconductors, power transistors, or other suitable semiconductor devices.
    [0034] Power converter 26 is controlled by control system 40. A generator controller controller 48 of control system 40 may have gate operating mechanisms and an analog to digital converter (ADC) 50, a microprocessor 52 electrically coupled to the gate operating mechanisms 50, and memory 54 electrically coupled to the microprocessor 52 and having stored therein operating instructions for the microprocessor 52. The base of each IGBT 842 is electrically coupled to a respective gate operating mechanism 50 which is dedicated to that IGBT 84-2 and can provide a low DC voltage (eg 24 VDC) to turn that IGBT 84-2 on and off. Therefore, there may be a port operating mechanism 50 for each IGBT 84-2 of the power converter 26. The port operating mechanisms 50 for the IGBT 84-2 of the power converter 26 are under the control of the microprocessor 52, which can employ a pulse width modulation control scheme to control those operating mechanisms of the logic gates 50 and the IGBT 84-2 of the power converter 26 to supply electrical power on the DC bus 28 in the generator 24 generation mode. and removes electrical power from the DC bus 28 in the generator 24 motor operating mode. In the exemplary embodiments, space vector modulation can be used. However, it should be understood, that any known pulse width modulation scheme for drive systems can be used. Therefore, for reasons of simplicity, the pulse width modulation scheme will not be described in greater detail.
    Motor 32 can be configured as a three-phase reluctance (SR) motor having three phase windings 42a, 42b and 42c as shown in Fig. 2, or it can be an AC PM or Induction PM motor (not shown). Each power inverter 30 is electrically coupled between the motor 32 and the rails 44, 46 of the DC bus 28. The power inverter 30 can be configured, for example, as a DC to AC inverter to convert DC power from the bus. from DC 28 to three-phase AC power to motor 32, and vice versa. The digital circuit voltages for each of the motor phase windings 42a, 42b and 42c in the power inverter 30 for the motor 32 are denoted as Vdig_phA for phase A voltage, Vdig_phB for phase B voltage, and Vdig_phC for the phase C voltage. For each phase of the voltage, Vdig_phA, Vdig_phB and Vdig_phC, a pair of high-side and low-side switch packets 94a, 94b are placed in series across the DC supply bus, and are switched ON and OFF to generate energy through each phase winding.
    [0036] As used in this document, switching status indicates whether an uncompromised or properly functioning semiconductor device is active (“ON” or “closed”) or inactive (“OFF or “open”). Failure of a semiconductor device to change state can result in a semiconductor device failing in an open state or a closed state, for example.
    [0037] The power inverter 30 may include pairs of high-side and low-side switching packages 94a and 94b. Each high-side switch package 94a includes a diode 94-1a, an insulated bipolar junction transistor (IGBT) 94-2a, and a diode power diode 96. Each low-side switch package 94b includes a diode 94- 1b, an IGBT 94-2b and a power diode 96. Pairs of switching packets 94a, 94b may be electrically coupled respectively to the phase windings 42a, 42b and 42c of the motor 32. As such, the power inverter 30 is represented as having three sections, 31a, 31b and 31c, each associated with one of the phase windings 42a, 42b and 42c. Sections 31a, 31b and 31c allow individual control of each individual phase A, B and C. In this configuration, for each section 31a, 31b and 31c, a high side switching packet 94a and a low side switching packet 94b are connected via a respective motor phase winding 42a, 42b and 42c. The high side switch pack 94a is electrically coupled to the positive DC rail 44, and the low side switch pack 94b is electrically coupled to the negative DC rail 46. When the proper voltage is applied to the base of an IGBT 94- 2a and/or 92b of the power inverter 30, the IGBT 94-2a and/or 94-2b (switch) can be activated and the collector can be electrically coupled to the emitter to supply electrical power to the respective winding 42a, 42b or 42c . Power inverter 30 can be operated in reverse if motor 32 is to operate as a generator. An example of energy flow situations is represented in more detail in Fig. 3.
    [0038] The power inverter 30 is controlled by the control system 40. A motor controller 56 of the control system 40 may have gate operating mechanisms 58, a field programmable gate array 60 (FPGA) electrically coupled to the mechanisms operating instructions 58, a microprocessor (e.g., digital signal processor) 62 electrically coupled to the FPGA 60, and memory 64 electrically coupled to both the FPGA 60 and the microprocessor 62 and having stored therein operating instructions for the FPGA 60 and microprocessor 62. The base of each IGBT 94-2a, 94-2b is electrically coupled to a respective gate operating mechanism 58 which is dedicated to that IGBT 94-2a, 94-2b and can provide a low DC voltage ( eg 24 VDC) to activate and deactivate that IGBT 94-2a, 94-2b. The port operating mechanisms 58 are under the control of the FPGA 60 which may employ an SR motor control scheme to control the port operating mechanisms 58, the IGBTs 94-2a, 94-2b, and thus, the motor 32 (including varying amplitudes and frequencies for motor windings 42a, 42b, 42c) in order to vary the torque emitted from motor 32 when motor 32 is in its operating mode or to vary the electrical generating capacity of the motor 32 when motor 32 is in its braking mode. As stated above, it can be appreciated that the drive system 12 may have more than one motor 32 and appended inverter 30 and current sensor(s) 38 incorporated therein, and the control system 40 may have a motor controller 56 for each. power inverter 30 to control that inverter 30, although only such inverter 30 and motor controller 56 are discussed and shown.
    [0039] Optionally, the drive system 12 may include an electronic brake module 22 to control use of a brake resistor 70 to dissipate electrical energy from the DC bus 28. The electronic brake module 22 can be electrically coupled between rails 44, 46 as shown. The voltage of the digital circuit in the drive system 12 of the electronic brake module 22 is shown as Vdig_Brake. Brake electronics module 22 may include a switching package 74, with a diode 74-1 and an insulated bipolar junction transistor (IGBT) 74-2 and a diode 76. Diode 76 may be in parallel with the brake resistor 70, When the appropriate voltage is applied to the base of the IGBT 74-2 of the electronic brake module 22, the IGBT 74-2 can be activated and the collector can be electrically coupled to the emitter to allow dissipation of electrical energy through the braking resistor 70. The gate operating mechanism for the IGBT 74-2 of the brake electronic module 22 outputs a brake resistor control signal in the form of, for example, a pulse-width modulated voltage signal that applies to which it applies the voltage to the base of the IGBT 74-2 switching, the voltage signal being pulse width modulated according to an active braking duty cycle to put the braking resistor 70 in the ON state, to dissipate electrical energy from of the DC bus 28, and in the state that of OFF correspondingly.
    [0040] The electronic brake module 22 is controlled by the control system 40. The door operating mechanism for the IGBT 74-2 of the electronic brake module 22 may be one of the door operating mechanisms 58 of the motor controller 56 Such gate operating mechanism 58 for the IGBT 74-2 may be under the control of the FPGA 60 of the motor controller 56 to control that gate operating mechanism 58, the IGBT 74-2, and the braking resistor 70. In other exemplary embodiments, the gate operating mechanism for the IGBT 74-2 may be one of the gate operating mechanisms 50 of the generator controller 48. In such a case, that gate operating mechanism 50 may be under control of the microprocessor 52 of the generator controller 48 to control that gate operating mechanism 50, the IGBT 74-2, and the braking resistor 70.
    [0041] The drive system 12 may have one or more voltage sensors coupled to the positive DC rail 44 of the DC bus 28 to detect the voltage of the DC bus. The DC bus voltage is the voltage between rails 44 and 46. In some exemplary embodiments, voltage sensors are also coupled to the negative DC rail 46 of the DC bus 28 and configured to detect the phase voltages for the A phases. , B, and C. Voltage sensors 36 can be stand-alone sensors or can be incorporated into any of controllers 48, 56 in the control system. For example, one voltage sensor 36 can be for generator 24 and another voltage sensor 36 can be used for motor control and pole voltage measurements. Voltage sensor 36 can send a signal to control system 40 including the perceived DC bus voltage.
    [0042] A 700 DC link capacitor can be provided between rails 44, 46. The 700 capacitor can be configured, for example, as a capacitor bank.
    [0043] In alternative embodiments, the windings 42a, 42b and 42c may be replaced by or represent an inductor.
    [0044] Referring now to Fig. 3, a detail of a section 3a of the power inverter 30 is shown describing the positive and negative current flow through a section 31a to a motor phase 32. While section 31a is illustrated in Fig. 3, it should be understood that sections 31b and 31c operate in a similar manner. Therefore, for reasons of simplicity, sections 31b and 31c will not be described. In a first operational mode, ie supplying positive current to a phase of motor 32, the high side IGTB 94-2a and the low side IGBT 94-2b are activated, such that the phase current flows in a 510 direction through the Switching packet on the disabled side. Because of the inductance of winding 42a, current continues to flow, coming through diode 96. It is noted that when current is quickly controlled and reduced to below a threshold level then both switching packets (94a and 94b) are deactivated and Current flows from the motor winding to the DC bus via the low side diode 96 and high side diode 96. In this mode, the negative DC bus voltage is applied across the motor winding. When current is slowly reduced to the threshold level then only one of either of the two switching packages (94a and 94b) is deactivated and current flows freely in the motor winding. In this mode, zero voltage is applied across the motor winding.
    [0045] In a second operating mode, ie supplying negative current to a phase of motor 32, the low side IGBT 94-2b is in the ON state, and the IGBT 94-2a is closed, such that the phase current flows in a direction 512 (except for SR machine as in SR machine there is no reverse current through the motor winding) through the low side switch 94b, returning the trapped magnetic energy to the DC bus 28. The energy pulse is short-lived, and then the IGBT 94-2b is disabled. Because of the inductance of winding 42a, current continues to flow outward through diode 96. This occurs for each of the 3 phases, A, B, and C; that is, in each section 31a, 31b and 31c.
    [0046] Exemplary modalities use these characteristics of inverter-powered electrical machine systems operating system 12 in a low-voltage pre-drive mode. In a method according to an exemplary embodiment, the control system 40 uses measurements of perceived signal levels to determine if there is a system failure. It should be understood that "signal level" can refer to either a measured phase voltage or a measured phase current. It is possible to convert a measured phase voltage to a phase current with a transconductance amplifier or trans-resistance amplifier (eg operational amplifier plus a resistor). For reasons of simplicity, the first method is described using phase currents measured as signal levels. However, it should be understood that the first method can be implemented using measured phase voltages.
    [0047] Another example modality uses perceived voltage measurements at the AC midpoint measured between the high side and low side devices on an inverter leg with respect to the negative DC bus, as shown in Figs. 5 and 6. AC midpoint voltages are denoted as AC pole point voltages. For example, Vpole_A for phase A AC pole point voltage, Vpole_B for phase B AC pole point voltage, Vpole_C for phase C AC pole point voltage, and if present, Vpole_BC for circuit of electronic brake module. The perceived voltages are processed at the ADC 50, 58 which is built into the gate operating mechanisms (50, 58) of the control system 40. The converted digital data is sent to the relevant control card. Data from Vpole A, Vpole_B, Vpole_C, Vpole_BC is considered as ADC count data. This method compares the ADC count data to switching device signals to identify and troubleshoot the system.
    [0048] In both methods, once the fault type and location is determined, the control system 40 will decrease or eliminate all effects of the fault(s) that have occurred, and will reconfigure the drive system 12 as necessary for it to resume operation at an optimal level without further compromise in the system hardware, or an error message will be relayed to indicate that the fault requires repair before the drive system 12 can continue safe operation.
    [0049] The first method according to an example embodiment is described in more detail below and shown in Figs. 4A - 4C.
    [0050] In step 100, the first step in control system 40 (diagnostic system) determines whether the DC bus is operating at a VT test voltage, ie, a low voltage used for the test mode (10 volts or any less). For example, the test voltage VT can be any voltage between 10V and 25V. At a DC bus voltage of 10 V, pre-trigger diagnosis can run slower and 25 V DC bus voltage, pre-trigger diagnosis can run faster. A DC bus voltage of 10V can be used for large electrical machines powered by inverter power and 25V can be used for small electrical machines powered by inverter power. A 32 motor inductance goes down as its power goes up. Low voltage (10 V) pre-drive diagnosis can be used for a low inductance machine to reach a faster overcurrent limit and high-voltage (25 V) pre-drive diagnosis can be used for a larger machine inductance.
    [0051] If the DC bus is a voltage greater than the VT test voltage, control system 40 diagnostics will not be performed in step 100a. If the DC bus is operating at or below the VT test voltage, the control system 40 enters a test mode, then in step 101, the control system 40 determines whether the DC bus voltage is less than the limit voltage VTH (eg 5 volts). If the DC bus voltage is less than the threshold voltage VTH, the control system 40 determines that a capacitor in the binding capacitor 700 has failed, and in step 200 the control system 40 sends an error to a register indicating that the capacitor failed. If control system 40 is in test mode, then at step 102, control system 40 sets an A-phase high side overcurrent value (eg, 10 amps). The overcurrent value is determined based on a vehicle's DC bus voltage diagnostic allowable time. In step 103, the phase A high side IGBT is set ON and the phase B low side IGBT is activated by the control system 40.
    [0052] In step 104, the control system 40 determines whether there is an overcurrent fault on the high side of phase A using current sensor 38 for phase A. If the control system 40 determines there is an overcurrent fault on the side high of phase A at step 201, the control system 40 determines whether the DC bus voltage has dropped below the threshold voltage VTH. If the DC bus voltage is below the threshold voltage VTH, this indicates that the low side IGBT of phase A is also ON, due to the fault. At step 202, control system 40 indicates that there is a shorted switch in control system 40 and provides a system alert to the FPGA 60 of the failure. If, in step 201, the DC bus voltage has not dropped below 5 volts, then in step 203, the control system 40 monitors the high side of phase A overcurrent to determine whether the high side of phase overcurrent fault The lasts for at least a TTH timeout (eg 10 ms). If the high side overcurrent of phase A lasts for at least the timeout TTH, then in step 204, the control system 40 determines that an open terminal system fault has occurred, indicating that current is not flowing, and that the machine is therefore not connected to the inverter. A system alert is provided to the FPGA 60 about the failure. If the A-phase high side overcurrent does not last for at least the TTH timeout, then the method proceeds to step 105.
    [0053] If in step 104, if the high side overcurrent of phase A does not experience a fault, then in step 105, the control system 40 checks to ensure that the DC bus voltage is equal to or less than the voltage test VT to ensure that the control system 40 is in test mode before proceeding with the pre-trigger test. If the DC bus voltage is not equal to or less than the test voltage VT, then control system 40 stops the method in step 105a. If the DC bus voltage is less than or equal to the VT test voltage, then in step 106, the control system 40 sets the high side overcurrent value of phase B (eg, 10 amps). In step 107, the control system 40 disables the high side IGBT of phase A and low side IGBT of phase B, and sets the low side IGBT of phase A and high side IGBT of phase B to ON state .
    [0054] In step 108, the control system 40 determines if there is an overcurrent fault on the high side of phase B, then in step 301, the control system 40 determines whether the DC bus voltage has dropped below the threshold voltage VTH . If the DC bus voltage is below the threshold voltage VTH, the control system 40 determines that the B-phase underside IGBT is also in the ON state, due to a fault. At step 302, the control system 40 indicates that there is a shorted switch (B-phase low side IGBT) in the drive system 12 and provides a system alert to the FPGA 60 of the failure. If, in step 301, the DC bus voltage has not dropped below 5 volts, then in step 303, control system 40 monitors the phase B high side overcurrent to determine whether the phase B high side overcurrent lasts. for at least the TTH timeout. If the phase B high side overcurrent lasts for at least the timeout TTH, then in step 304, the control system 40 determines that an open terminal system fault has occurred, indicating that current is not flowing, and that the machine, is therefore not connected to the inverter. A system alert is provided to the FPGA 60 about the failure. If the B-phase high side overcurrent fault does not last for at least the TTH timeout, then the method proceeds to step 109.
    [0055] In step 108, if the control system 40 determines that the high side overcurrent of phase B does not experience a fault value, then in step 109, the control system 40 checks to ensure that the DC bus voltage is equal to or less than the VT test voltage to ensure that the control system 40 is in test mode before proceeding with the pre-trigger test. If the DC bus voltage is not equal to or less than the VT test voltage, then control system 40 stops the method in step 109a. If the DC bus voltage is equal to or less than the VT test voltage, then in step 10, the control system 40 sets the high-side A-phase overcurrent value (eg, 10 amps). In step 111, the phase A high side IGBT is set to the ON state and the phase C low side IGBT is activated by the control system 40.
    [0056] In step 112, if the control system 40 determines that there is an A-phase high side overcurrent fault, then in step 401, the control system 40 determines whether the DC bus voltage has dropped below the threshold voltage VTH. If the DC bus voltage is below the threshold voltage VTH, the control system 40 determines that the A-phase low side IGBT is also in the ON state, due to the fault. At step 402, control system 40 indicates that there is a shorted switch in drive system 12 and provides a system alert to the FPGA 60 of the failure. If, in step 401, the DC bus voltage has not dropped below the threshold voltage VTH, then in step 403, the control system 40 monitors the high side overcurrent of phase A to determine whether the high side overcurrent fault of the phase A lasts for at least the TTH timeout. If the A-phase high side overcurrent fault lasts for at least the timeout TTH, then in step 404, the control system 40 determines that an open terminal system fault has occurred, indicating that current is not flowing, and that the machine is therefore not connected to the inverter. A system alert is provided to the FPGA 60 about the failure. If the A-phase high side overcurrent fault lasts for at least the TTH timeout, then the method proceeds to step 3.
    [0057] If in step 112, the high side overcurrent of phase A does not experience a fault, then in step 113 the control system 40 checks to ensure that the DC bus voltage is equal to or less than the voltage of VT test to ensure that the control system 40 is in test mode before proceeding with the pre-trigger test. If the DC bus voltage is equal to or less than the VT test voltage, the control system stops the method in step 113a. If the DC bus voltage is equal to or less than the VT test voltage, then in step 114, the control system 40 sets an overcurrent value on the high side of phase C (eg, 10 amps) . In step 115, the control system 40 disables the phase A high side IGBT and the phase C low side IGBT, and sets the phase A low side IGBT and the phase C high side IGBT to the state of ON.
    [0058] If in step 116, the control system 40 determines that there is an overcurrent fault on the high side of phase C, then in step 501, the control system 40 determines whether the DC bus voltage has dropped below the threshold voltage VTH. If the DC bus voltage is less than the threshold voltage VTH, the control system 40 determines that the C-phase underside IGBT is also in the ON state, due to the fault. At step 502, the control system 40 indicates that there is a shorted switch (eg, IGBT 94-2a on the high side of phase C) in the drive system 12 and provides a system alert to the FPGA 60 about the fault . If, in step 501, the DC bus voltage has not dropped below the threshold voltage VTH, then in step 503, the control system 40 monitors the high side overcurrent of phase C to determine whether the high side overcurrent fault of the phase C lasts for at least the TTH timeout. If the C-phase high side overcurrent fault lasts for at least the timeout TTH, then in step 504, the control system 40 determines that an open terminal system fault has occurred, indicating that current is not flowing, and that the machine is therefore not connected to the inverter. A system alert is provided to the FPGA 60 about the failure. If the C-phase high side overcurrent fault does not last for at least the TTH timeout, the method proceeds to step 117.
    [0059] If in step 116, if the high side overcurrent of phase C does not experience a fault value, then in step 117 the control system 40 checks to ensure that the DC bus voltage is equal to or less than the set the VT test voltage to ensure that the control system 40 is in test mode before proceeding with the pre-trigger test. If yes, then the test mode will proceed to capacitor check in step 120, inverter check in step 130, generator check in step 140, cable check in step 150, etc. If the DC bus voltage is not equal to or less than the VT test voltage the control system stops the method in step 117a.
    [0060] If in step 117, the control system 40 determines that the DC bus voltage is not equal to at least the test voltage VT, the control system 40 continues to monitor the DC bus voltage until it is equal to at least the test voltage VT. If, at step 117, the DC bus voltage is still equal to the test voltage VT, then the control system 40 resets the IGBTs from step 115. At step 120, the control system 40 performs a diagnostics check of pre-drive capacitors in the drive system 12. A system alert is provided for the FPGA 60 of any faults. At step 130, the control system 40 performs a pre-start diagnostics check of the inverter system 30, a system alert is provided to the FPGA 60 about any faults. At step 140, the control system 40 performs a pre-start diagnostics check of the generator system 24. A system alert is provided to the FPGA 60 of any faults. At step 150, the control system 40 performs a pre-start diagnostics check of the electronic brake module 22 system. A system alert is provided to the FPGA 60 of any faults. At step 160, the control system 40 performs a pre-triggering diagnostics check of the system cables. A system alert is provided for the FPGA 60 of any failures. When all system pre-start diagnostics are successfully completed in step 170, and the drive system 12 appears to be operating correctly, full power proceeds.
    [0061] A second method of failure analysis according to an example embodiment is described in more detail below and the differences in voltage measurements are shown in Figs. 5 and 6. While FIGS. 5 and 6 are used to describe the second method, it is to be understood that the systems illustrated in Figs. 5 and 6 can be used in implementing the first method illustrated in Figs. 4A - 4C.
    [0062] The second method uses perceived voltage measurements at the AC midpoint measured between high-side and low-side devices on a drive leg with respect to a negative DC bus. In the example embodiments according to Fig. 5, an inverter leg can refer to a high-side switch (eg an IGBT in parallel with a diode) electrically connected with a low-side switch. A midpoint of a drive leg can be referred to as a drive pole point or AC point. These voltages are denoted as AC pole point voltages. For example, Vpole_A for phase A AC pole point voltage, Vpole_B for phase B AC pole point voltage, Vpole_C for phase C AC pole point voltage, and if present, Vpole_BC for modulo circuit electronic brake. The inverter pole point is used to connect the inverter to the machine (eg motor). The voltages across each phase A, B and C of the motor winding are measured by voltage sensors (not shown).
    [0063] In an SR motor system such as the SR motor system shown in Fig. 6, a leg of the inverter may refer to a high-side switch electrically connected with a low-side diode and may also refer to to a high-side diode electrically connected with a low-side switch. The positive and negative voltages across each phase of the motor winding are measured: i.e., the voltage Vpole_A+ positive and the voltage Vpole_A- negative. The positive and negative voltages across each phase A, B and C of the motor winding are measured by voltage sensors (not shown).
    [0064] The perceived voltages are processed in the analog to digital converter (ADC) which is built into the gate operating mechanism (50, 58) of the control system 40. The converted digital data is sent to the relevant control card. Data from Vpole_A, Vpole_B, Vpole_C, Vpole_BC is considered as ADC count data.
    [0065] For example, the port operation mechanism 58 can apply analog signals from 0 to 5V to the IGBTs. To be in the linear range, the door operating mechanism can use 0.5V to 4.5V. Therefore, if a high side IGBT is activated, the input voltage to the ADC will be 4.5V and if the low side IGBT is activated the input voltage to the ADC will be close to 0.5V. If no IGBT is activated, an inverter pole voltage will be close to 2.5V. A voltage perceived at an inverter pole point after processing by the front stage remains in the range of 0.5V and 4.5V. The perceived voltage can be converted into ADC count data. For example, 4.5V can equal 921 counts for a 10-bit ADC and 0.5V can equal 102 counts. Therefore, depending on the ADC counts it can be determined whether an IGBT has been activated. Once the IGBT is in the OFF state, a voltage reading will change as the current that was supplied by the IGBT is taken by a diode and the reading for the ADC will change.
    [0066] This method compares the ADC count data to switch device signals to identify and troubleshoot the drive system 12.
    [0067] FIG. 5 represents voltage measurement for a PM or AC induction machine for the second predrive failure detection method. Control system 40 is configured and wired as shown in Fig. 2. Therefore, for the sake of simplicity, the description of control system 40 will be omitted. For each voltage phase, Vpole_A, Vpole_B and Vpole_C, high-side and low-side switch packet pairs 94'a and 94'b are placed across the DC bus, and turned on and off to generate the three phases A, B and C. Each high-side switch package 94'a includes a diode 94-1a and an insulated bipolar junction transistor (IGBT) 94'-2a. Each 94'b low-side switching package includes a 94'-1b diode and a 94'-2b IGBT. Respective pairs of switching packets 94'a, 94'b can be coupled to a respective one of the phase windings between a positive DC power path 44' and a negative DC power path 46' of the DC bus 28' . As shown, two resistors Rbal are connected in series between the positive DC power rail 44' and the negative DC power rail 46' of the DC bus 28'. The base of each IGBT 94'-2a, 94'-2b is electrically coupled to a respective gate operating mechanism 58 which is dedicated to that IGBT 94'2a, 94'2b and can provide a low DC voltage (eg. , 24 VDC) to turn that IGBT 94'-2a, 94'-2b on and off. There are two possibilities of ADC counting, depending on when the switches (IGBT 94'-2a, 94'-2b) are commanded to be closed and/or open. These two possibilities are shown in table 1, below for 10-bit and 12-bit ADCs.
    [0068] It should be understood that table 1, as well as tables 2 - 5, can be produced from empirical data. For example, an electronic circuit can be placed between the inverter pole points (with respect to the negative DC bus) and an ADC input (analog to digital converter) on the door operation mechanism cards. The electronic circuit reduces voltages at the input ADC input to a maximum value of 5V and a minimum value of 0V. ADC count per volt is placed as: (1/(5V/2A10))
    [0069] Gate operating mechanism 58 provides ADC counts to a control card and the control card determines pole voltages values and then the pole voltages determined by the control card are looked against a switch state [ON or OFF or that was recently made with the switches (IGBTs enabled or disabled)] of the drive. The developed ADC count data becomes decision criteria for the control system 40 to decide a fault type in an inverter powered electrical machine and where the fault occurred.
    [0070] Control system 40 is configured to detect inverter fault (eg power inverter 30) if the ADC count data does not match one or more reference ranges (eg lookup tables 1 - 5 below) stored in memory 64 for corresponding switching states of semiconductor devices. Conversely, the control system is adapted to detect the absence of fault in the inverter (eg power inverter 30) if the ADC count data matches one or more reference intervals stored in memory 64 for corresponding switching states of semiconductor devices. Table 1: All switches are intact and AC PM or induction multi-phase machine is properly connected with inverter.

    [0071] The control system 40 can determine if the ADC count does not follow the pattern shown in table 1. If the ADC count does not follow the pattern shown in table 1, then a fault is declared by the control system 40. There seven different categories of faults that can be identified in the control system 40 using this detection method. The categories are as follows: Category A: DC Bus Failed to Short, Category B: DC Bus Failed to Open, Category C: IGBT Failed to Open, Category D: IGBT Failed to Short, Category E: Diode Failed to Open , Category F: Diode failed to short, Category G: Motor cable is not connected with pole inverter
    [0072] Once the control system 40 determines that there is a failure in the drive system 12, the failure can be identified as shown in table 2. Table 2: A failure exists in the induction Ac or PM electrical machine powered by inverter, either on the inverter or on the machine.



    [0073] FIG. 6 represents voltage measurement for an SR machine for the second pre-drive detection method. Control system 40 is configured and wired as shown in Fig. 2. Therefore, for the sake of simplicity, the description of control system 40 will be omitted. For each voltage phase, Vpole_ A, Vpole_ B, and Vpole_ C, a pair of high-side and low-side 94”a and 94”b switch packets are placed in series across the DC supply bus, and are activated and turned off to generate power through each phase winding. Each 94"a, 94"b switching package includes a 94"-a, 94"-1b diode, an insulated bipolar junction transistor (IGBT) 94"-2a, 94"-2b, and a 96 power diode ”. The 94"a high side switch package is electrically coupled to a 44" positive DC rail of a 28" DC bus, and the 94"b low side switch package is electrically coupled to a 46 negative DC rail ” of the DC bus 28”. Respective pairs of 94”a, 94”b switching packets can be coupled to a respective one of the SR motor winding phases, shown in Fig. 6 as Phase 1, Phase 2 and Phase N. The basis of each IGBT 94 ”-2a, 94”-2b is electrically coupled to a respective 58 gate operating mechanism which is dedicated to those IGBT 94”-2a, 94”-2b and can provide a low C voltage (eg 24 VDC) to turn those 94”-2a, 94”-2b IGBTs on and off. The 58 gate operating mechanisms are under the control of the FPGA 60 which can employ an SR motor control scheme - to control the 58 gate operating mechanisms, the 94”-2a, 94”-2b IGBTs, and so on. being the motor (including variation of amplitudes and frequencies for the motor windings), in order to vary the torque emitted from the motor 32. The ADC counting conditions for SR machines, for Vpole_A+, Vpole_A-, Vpole_B+, Vpole_B-, Vpole_C+, Vpole_C-, and Vpole_BC when all 94”a, 94”b switching packets are intact and the multi-phase SR machine is connected to the drive and operating correctly are shown in table 3, below for 10-bit ADCs and 12 bits. The SR motor control scheme can be any known SR motor operating scheme for drive systems. Therefore, for reasons of simplicity, the SR motor control scheme will not be described in greater detail. Table 3: All switches are intact and multi-phase SR machine is connected with inverter.

    [0074] The control system 40 can determine if the ADC count does not follow the pattern shown in table 3. If the ADC count does not follow the pattern shown in table 3, then the fault can be declared by the control system 40. There are seven different categories of faults that can be identified in the drive system using this detection method. The categories are as follows: Category A': CC bus has failed to short, Category B': CC bus has failed to open, Category C: IGBT has failed to open, Category D': IGBT has failed to short, Category E': Diode failed open, Category F': Diode failed short, Category G': Motor cable is not connected with pole inverter.
    [0075] Once the control system 40 has determined that there is a failure in the drive system, the video control system 40 proceeds with detection if there is a failure in the DC bus, as shown in table 4. Table 4: Detecting failure on the DC bus in a multi-phase SR machine.

    [0076] If the DC bus passes the test, there is no DC bus fault, and the control system 40 proceeds with identifying the fault location in the drive, machine and/or cable connecting the machine to the drive. Table 5: Detecting failure in phase A of SR machine with DC bus passed as in table 4.


    [0077] When the analysis in table 5 was completed for phase A by control system 40, control system 40 performs the analysis for phases B and C, with switches (IGBTs and diodes) for phases B and C used, respectively, to pick up appropriate voltages and pole point and ADC counts. A fault detection method for electronic brake module IGBTs in SR machines can be the same as stated in table 2 above.
    [0078] Any of tables 1 to 5, inclusive, may be structured as one or more lookup tables, files, database, data records or other data structure that are stored in memory 64 of the control system 40.
    [0079] In any of the tables, there are two possibilities or illustrative permutations of ADC count depending on when switches (IGBTs in inverter) are commanded to be closed and/or open. The above possibilities are listed in the table below for 0 bit or 12 bit analog to digital converter (ADC) (eg 14 analog to digital converter). In tables 1 to 5, inclusive, through sensing alternating current node voltages (inverter midpoint voltage with respect to the negative direct current bus) and knowing ADC counts for, Vpole_A, Vpole_B, Vpole_C, and Vpole_BC, the following faults can be detected in inverter powered electrical machine systems: (1) any one or pair of switching transistors (eg, IGBTs) has failed to short the inverter; (2) any switching transistor (eg, IGBT) has failed to open in the inverter; (3) any diode (eg protection diode) has failed to short or failed to open in the drive; (4) any capacitors have failed to short; (5) any cable between inverter or machine has failed to short or has failed to open; (6) any machine winding has failed to short or has failed to open; (7) any brake circuit transistor (eg, brake electronics module IGBT) or diode has failed to open or has failed to short; and (8) brake grid resistor and/or cable failed to open or failed to short.
    [0080] Exemplary modalities being thus described, it will be obvious that they can be varied in many ways. Such variations are not to be considered as a departure from the scope of the exemplary embodiments, and all such modifications, as would be obvious to one skilled in the art, are intended to be included within the scope of the claims.
    权利要求:
    Claims (14)
    [0001]
    1. Drive system (12), characterized in that it comprises: a machine including a plurality of phases and configured to generate power based on a plurality of phase currents, each respectively associated with a plurality of phases; a direct current (DC) bus (28) operatively connected to the machine, the DC bus (28) including: a high-side line (44); a low side line (46); and, an inverter (30) including a plurality of switching systems (31a, 31b, 31c) operatively connected between the high side line (44) and the low side line (46) each of the plurality of switching systems (31a, 31b, 31c) configured to output a respective one of the plurality of phase currents; each of the switching systems (31a, 31b, 31c) comprising: a high side switching system operatively connected to the high side line (44), the high side switching system being configured to output the phase current associated with the at least one of the plurality of switching systems (31a, 31b, 31c); and, a low-side switching system operatively connected to the low-side line (46); a controller (56) operatively connected to the DC bus (28) and the machine, the controller (56) configured to determine if a fault exists in the drive system (12) based on a plurality of phase currents and at a DC bus voltage (28), the DC bus voltage (28) being a voltage between the high side line (44) and the low side line (46); and, a plurality of current sensors (38) configured to respectively measure the plurality of phase currents and output measurement signals including the measured phase currents, the controller (56) being configured to receive the measurement signals, wherein the controller (56) is configured to determine an overcurrent value for a particular high side switching system of the switching systems (31a, 31b, 31c), activate the particular high side switching system, determine if an overcurrent fault exists based on the measured phase current and the overcurrent value.
    [0002]
    2. Drive system (12) according to claim 1, characterized in that the controller (56) is configured to determine whether the DC bus voltage (28) is below a threshold voltage if the overcurrent fault exist.
    [0003]
    3. A drive system (12) according to claim 2, characterized in that the controller (56) is configured to determine that the at least one of a plurality of switching systems (31a, 31b, 31c) is in short if the DC bus voltage (28) is below the threshold voltage based on the overcurrent fault.
    [0004]
    4. Drive system (12) according to claim 1, characterized in that the controller (56) is configured to determine whether the overcurrent fault exceeds a timeout.
    [0005]
    5. Drive system (12) according to claim 4, characterized in that the controller (56) is configured to determine whether the inverter (30) is operatively connected to the machine based on the overcurrent fault .
    [0006]
    6. Drive system (12) according to claim 1, characterized in that the machine is a permanent magnet motor (PM) or an alternating current (AC) induction motor.
    [0007]
    7. Drive system (12), characterized in that it comprises: a machine including a plurality of phases and configured to generate power based on a plurality of phase currents, each respectively associated with a plurality of phases; a direct current (DC) bus (28) operatively connected to the machine, the DC bus (28) including: a high-side line (44); a low side line (46); and, an inverter (30) including a plurality of switching systems (31a, 31b, 31c) operatively connected between the high side line (44) and the low side line (46) each of the plurality of switching systems (31a, 31b, 31c) configured to output a respective one of the plurality of phase currents and a phase voltage; and, a controller (56) operatively connected to the DC bus (28) and the machine, the controller (56) configured to respectively apply voltages to the plurality of switching systems (31a, 31b, 31c), as phase voltages emitted by the plurality of switching systems (31a, 31b, 31c) respectively based on the applied voltages, the controller (56) including: an analog to digital converter (ADC) configured to measure the phase voltages emitted by the plurality of switching systems (31a, 31b, 31c) and generating count data based on the measured phase voltages; and, the controller (56) configured to determine if a fault exists in the drive system (12) based on the counter data.
    [0008]
    8. Drive system (12) according to claim 7, characterized in that the controller (56) is configured to store a table, the table including operating information representing an operation of the drive system (12) with no faults, and controller 56 is configured to determine if a fault exists based on the counter data and operating information.
    [0009]
    9. Drive system (12) according to claim 8, characterized in that the controller (56) is configured to determine a fault type based on the counting data.
    [0010]
    10. Drive system (12) according to claim 9, characterized in that the controller (56) is configured to determine the type of fault based on the count data and a DC bus voltage (28) .
    [0011]
    11. Drive system (12) according to claim 8, characterized in that the machine is a permanent magnet motor (PM) or an alternating current (AC) induction motor.
    [0012]
    12. Drive system (12) according to claim 8, characterized in that the controller (56) is configured to determine if a DC bus failure (28) exists based on the counting data.
    [0013]
    13. Drive system (12) according to claim 11, characterized in that the controller (56) is configured to determine a fault location if the controller (56) determines that there are no DC bus faults (28 ).
    [0014]
    14. Drive system (12) according to claim 15, characterized in that the machine is a permanent magnet motor (PM), a switched reluctance motor (SR) or an alternating current (AC) motor of induction.
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    同族专利:
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    法律状态:
    2018-12-18| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|
    2019-07-23| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|
    2020-06-09| B06A| Patent application procedure suspended [chapter 6.1 patent gazette]|
    2021-02-09| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|
    2021-04-20| B16A| Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 23/01/2012, OBSERVADAS AS CONDICOES LEGAIS. |
    优先权:
    申请号 | 申请日 | 专利标题
    US201161446539P| true| 2011-02-25|2011-02-25|
    US61/446539|2011-02-25|
    US201161454690P| true| 2011-03-21|2011-03-21|
    US61/454690|2011-03-21|
    US13/052767|2011-03-21|
    US13/052,767|US8810189B2|2011-02-25|2011-03-21|Machine systems including pre-power diagnostics|
    PCT/US2012/022143|WO2012115736A1|2011-02-25|2012-01-23|Machine systems including pre-power diagnostics|
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